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Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for OC-12/STM-4 and GbE
ACS8946 JAM PLL
DATASHEET
ADVANCED COMMUNICATIONS Introduction
FINAL Features
The ACS8946 JAM PLL is a Jitter-Attenuating, Multiplying differential Phase-Locked Loop, for generating low jitter output clocks compliant up to SONET OC-12 and STM-4 622.08 MHz specifications. Its primary function is to clean up clock jitter for high performance optical line cards with OC-12 framers and serializers. It also provides reference switching functionality for line card protection, and frequency translation. Typical output jitter generation is within OC-12/STM-4 specifications, at 2.8 ps rms, making it an ideal dejittering solution for use with Semtech clock and line card parts: ACS8510, ACS8520, ACS8522 and ACS8530. The ACS8946 can also be used as a basic line card protection device in some applications. The ACS8946 JAM PLL has two differential, frequency programmable, LVPECL reference inputs and one differential sync input. It has four outputs, programmable as LVPECL or CML, and frequency programmable to any common SONET/SDH rate i.e. 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz and 622.08 MHz. Jitter cleaning of Gigabit Ethernet (GbE) 125 MHz and 156.25 MHz is also possible, with output frequency multiplication up to 625.00 MHz available. The device's operating bandwidth (and consequently the jitter attenuation point relating to this bandwidth) is fully configurable, and is set by external passive components.
Note...For items marked [1],[2], etc. references are given in full in the Reference Section on page 38.
Meets rms jitter requirements of: Telcordia GR-253[8] for OC-3 and OC-12 ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates ETSI EN300-462-7[1]/EN302-084[2] up to STM-16 rates PLL bandwidth and jitter peaking fully adjustable-- supports PLL loop bandwidths from 2 kHz for superior input jitter filtering
Typical jitter generation down to:
0.3 ps rms for 250 kHz to 5 MHz band for G.813, or EN300 462, at STM-4 (OC-12) rates 2.8 ps rms for 12 kHz to 20 MHz band (against 4.02 ps rms for GR-253-CORE at OC-48 rate) ITU, ETSI and Telcordia frequency band results shows exceptional performance in a "Real World" environment (low PLL bandwidth of 2 KHz and a typical input from an ACS8525 partner IC): 0.4 ps rms for 250 kHz to 5 MHz band for G.813, or EN300 462, at STM-4 (OC-12) rates 2.8 ps rms for 12 kHz to 20 MHz band Tracking range 400 ppm about a wide range of input frequencies Manual or automatic control of reference selection External feedback option LOS alarms for each input, and for selected reference 3.3 V operation, - 40 to +85C temperature range Small outline leadless 7 mm x 7 mm QFN48 package Lead (Pb)-free version available (ACS8946T), RoHS[11] and WEEE[12] compliant
Block Diagram
Figure 1 Simplified Block Diagram of the ACS8946 JAM PLL
RESETB 1 x LVPECL Differential Sync Input SYNC 2 x LVPECL Differential CLK1 Input References Programmable: CLK2 19.44 MHz to 156.25 MHz Re-timing Loop Filter VC 1 x CMOS Single-ended Sync Output SYNC_OUT
Input Selector Divider PFD Charge Pump 2.5 GHz VCO
Device Configuration Select: CFG_IN[7:0] CFG_OUT2
Note: LOS alarm outputs are also used for device config. select
Control and Monitor
Clock Input Configuration for: - Manual selection - Auto Ref selection - External feedback mode (SEL_CLK2, AUTO_SEL)
Lock Alarm (LOCKB) LOS Alarms for: - CLK1 (ALARM1_CO0) - CLK2 (ALARM2_CO1) - Currently selected reference (ALARMC_CO3)
4 x LVPECL or CML Output Clocks, Independently Programmable Frequency Dividers OUT[4:1] from: 625.00 MHz 622.08 MHz Clock 311.04 MHz Drivers 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz 125 MHz 156.25 MHz Frequency Select Others Ethernet rates (RATE[2:1]A, RATE[2:1]B) available using divider
F8946D_004Blockdiag_06
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Table of Contents ADVANCED COMMUNICATIONS Table of Contents
Section
ACS8946 JAM PLL
DATASHEET
Page
FINAL
Introduction................................................................................................................................................................................................ 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 3 Pin Description........................................................................................................................................................................................... 3 Description ................................................................................................................................................................................................. 8 Inputs ..................................................................................................................................................................................................8 Outputs ...............................................................................................................................................................................................8 Clock Multiplication ...........................................................................................................................................................................9 Voltage Controlled Oscillator.............................................................................................................................................................9 Jitter Filtering......................................................................................................................................................................................9 Jitter Filtering: Partnering with Semtech Line Card Protection Parts .......................................................................................... 10 Input Jitter Tolerance...................................................................................................................................................................... 10 Jitter Transfer .................................................................................................................................................................................. 10 Phase Noise Performance.............................................................................................................................................................. 11 Lock Detector .................................................................................................................................................................................. 11 PLL Bandwidth Setting ................................................................................................................................................................... 12 RC Components Required to Achieve Bandwidth at Given Input Frequencies (Tables 6 to 9). ...................................... 12 Source Switching - State Diagram ................................................................................................................................................. 13 Configuration................................................................................................................................................................................... 13 Output Configuration............................................................................................................................................................. 13 Example Configuration.......................................................................................................................................................... 14 Output Jitter..................................................................................................................................................................................... 21 System Reset .................................................................................................................................................................................. 21 Layout Recommendations ............................................................................................................................................................. 21 Applications ..................................................................................................................................................................................... 22 Example Schematic ........................................................................................................................................................................ 23 Electrical Specifications ......................................................................................................................................................................... 24 Maximum Ratings ........................................................................................................................................................................... 24 Operating Conditions ...................................................................................................................................................................... 25 Thermal Characteristics ................................................................................................................................................................. 25 AC Characteristics........................................................................................................................................................................... 25 DC Characteristics .......................................................................................................................................................................... 26 Input and Output Interface Terminations...................................................................................................................................... 27 Jitter Performance .......................................................................................................................................................................... 30 Input/Output Timing ....................................................................................................................................................................... 35 Package Information .............................................................................................................................................................................. 36 Thermal Conditions......................................................................................................................................................................... 37 References and Related Standards ...................................................................................................................................................... 38 Abbreviations .......................................................................................................................................................................................... 38 Revision Status/History ......................................................................................................................................................................... 39 Trademark Acknowledgements ............................................................................................................................................................. 39 Notes ....................................................................................................................................................................................................... 39 Ordering Information .............................................................................................................................................................................. 40 Disclaimers...................................................................................................................................................................................... 40 Contacts........................................................................................................................................................................................... 40
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Pin Diagram
Figure 2 ACS8946 Pin Diagram
SYNC_OUT RATE2A VDDOSC RATE1B RATE2B RATE1A RESETB VDDP2 SYNCN VSSOSC SYNCP
FINAL
DATASHEET
39
42
48
46
43
40
45
44
38
1 2 3 4 5 6 7 8 9
VDDO1 OUT1N OUT1P VDDO2 OUT2N OUT2P VDDO3 OUT3N OUT3P
37
41
47
IC1
36 35 34 33 32 31 30
VCN VCP VDDARF AUTO_SEL SEL_CLK2 CLK2P CLK2N VDDP1 CLK1P CLK1N VDDADIV CFG_IN7
ACS8946
29 28 27 26 25
10 VDDO4 11 OUT4N 12 OUT4P
13 ALARM1_CO0
14 ALARM2_CO1
15 CFG_OUT2
19 CFG_IN1
20 CFG_IN2
22 CFG_IN4
18 CFG_IN0
CFG_IN3
23 CFG_IN5
Dimensions: 7 mm x 7 mm Lead Pitch: 0.5 mm (Leads centered on package)
21
24
17
CFG_IN6
LOCKB
Connect large central pad (Pin 49 VSSO) to GND
16 ALARMC_CO3
F8944_D_002PINDIAG_01
Pin Description
Table 1 Power Pins
Pin No. 1, 4, 7, 10 26 29 43 34 38 39 49 Symbol VDDO1, VDDO2, VDDO3, VDDO4 VDDADIV VDDP1 VDDP2 VDDARF VDDOSC VSSOSC VSS0 I/O P Type Description Supply Voltage: Independent supplies to power each clock output (differential pair of pins) OUT1N/P to OUT4N/P respectively. +3.3 Volts 5%. To disable an output and save power, tie associated VDD to 0V. Supply Voltage: Supply for internal Dividers in VCO loop, kept as an isolated supply to allow for low supply noise for the output divider stages. +3.3 Volts 5%. Supply Voltage: Supply to differential inputs, alarm and config. pins. +3.3 Volts 5%. Supply Voltage: Supply to Sync input and Sync output pins, rate selection pins, input selection pins and reset pin. +3.3 Volts 5%. Supply Voltage: Supply for phase and frequency detector (PFD), kept as an isolated supply to allow for low supply noise. +3.3 Volts 5%. Supply Voltage: Supply input to the internal VCO. +3.3 Volts +5/-10%. Supply Ground: 0 V for the internal VCO. Supply Ground: Common 0 V. This is the central leadframe pad on the underneath of the package.
P P P P P P P
-
Note...A= Analog, I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD = LVTTL/LVCMOS input with pull-down resistor. Revision 3/November 2006 (c) Semtech Corp. Page 3 www.semtech.com
ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Table 2 Internally Connected (IC) Pin
Pin No. 37 IC1 Symbol I/O Type Description Internally Connected: Connect to ground.
FINAL
DATASHEET
Table 3 Functional Pins
Pin No. 2 Symbol OUT1N I/O O Type CML or LVPECL Description One of four CML or LVPECL differential outputs, partnered with pin 3; programmable at spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT1 and OUT2 only, output frequency can be instantly configured using Rate Selection pins (pins 47 and 48 for OUT1), from a set of four pre-configured "Available Rates". See"Configuration" on page 13. Output is on when VDD01 is supplied with 3.3 V, or off when VDD01 is tied to zero volts. If VDD01 is connected to 0 V remove external biasing resistors. CML or LVPECL differential output partnered with pin 2. See pin 2 description for more detail. One of four CML or LVPECL differential outputs, partnered with pin 6; programmable at spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT1 and OUT2 only, output frequency can be instantly configured using Rate Selection pins (pins 45 and 46 for OUT2), from a set of four pre-configured "Available Rates". See"Configuration" on page 13. Output is on when VDD02 is supplied with 3.3 V, or off when VDD02 is tied to zero volts. If VDD02 is connected to 0 V remove external biasing resistors. CML or LVPECL differential output partnered with pin 5. See pin 5 description for more detail. One of four CML or LVPECL differential outputs, partnered with pin 9; programmable at spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT3 and OUT4 only, the output frequency selection is controlled at power-up or on reset from a set of four pre-configured "Available Rates". See"Configuration" on page 13. Output is on when VDD03 is supplied with 3.3 V, or off when VDD03 is tied to zero volts. If VDD03 is connected to 0 V remove external biasing resistors. CML or LVPECL differential output partnered with pin 8. See pin 8 description for more detail. One of four CML or LVPECL differential outputs, partnered with pin 12; programmable at spot frequencies from 19.44 MHz up to 625.00 MHz. For outputs OUT3 and OUT4 only, the output frequency selection is controlled at power-up or on reset from a set of four pre-configured "Available Rates". See"Configuration" on page 13. Output is on when VDD04 is supplied with 3.3 V, or off when VDD04 is tied to zero volts. If VDD04 is connected to 0 V remove external biasing resistors. CML or LVPECL differential output partnered with pin 11. See pin 11 description for more detail. Activity alarm output for the CLK1P/CLK1N input reference clock. Active high; high indicating clock failure. It is also used to configure the device at power-up, where it is used as a configuration output pin, that may be connected to CFG_IN[0:7] input pins as required. See "Configuration" on page 13. Activity alarm output for the CLK2P/CLK2N input reference clock. Active high; high indicating clock failure. It is also used to configure the device at power-up time, where it is used as a configuration output pin, that may be connected to CFG_IN[0:7] input pins as required. See "Configuration" on page 13.
3 5
OUT1P OUT2N
O O
CML or LVPECL CML or LVPECL
6 8
OUT2P OUT3N
O O
CML or LVPECL CML or LVPECL
9 11
OUT3P OUT4N
O O
CML or LVPECL CML or LVPECL
12 13
OUT4P ALARM1_CO0
O O
CML or LVPECL LVTTL/ LVCMOS
14
ALARM2_CO1
O
LVTTL/ LVCMOS
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Table 3 Functional Pins (cont...)
Pin No. 15 Symbol CFG_OUT2 I/O O Type LVTTL/ LVCMOS LVTTL/ LVCMOS Description Configuration pin, used in the configuration on power-up of expected input clock frequency and Resync selection, by connecting to appropriate pin from the CFG_IN[0:7] pins as required. See "Configuration" on page 13. Activity alarm output for the currently selected input reference clock. Active high; high indicating clock failure. It is also used to configure the device at power-up, where it is used as a configuration output pin that may be connected to CFG_IN[0:7] input pins as required. See "Configuration" on page 13. Lock detect output. This is a pulse-width modulated output current, with each pulse typically +10 A. The output produces a pulse with a width in proportion to the phase error seen at the internal phase detector. This pin should be connected via an external parallel capacitor and resistor to ground. The pin voltage will then give an indication of phase lock: When low, the device is phase locked; when high the device has frequent large phase errors and so is not phase locked. The value of the RC components used determines the time and level of consistency required for lock indication. If LOCKB is disabled by configuration the LOCKB output is held low. Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 19 to set the available output rates as shown in Table 11. Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 18 to set the available output rates as shown in Table 11. Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 21 to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1 and OUT2 as in Table 10. Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power, or one of the configuration outputs at pins 13 to 16. This pin is used with pin 20 to set the input divider and output pad mode (CML or LVPECL) configuration for OUT1 and OUT2 as in Table 10. Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 23 to set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins 8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12. Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 22 to set the clock edge used for SYNC sampling, and the output clock frequency of OUT3 (pins 8 and 9) and OUT4 (pins 11 and 12), as shown in Table 12.
FINAL
DATASHEET
16
ALARMC_CO3
O
17
LOCKB
O
Analog
18
CFG_IN0
I
LVTTL/ LVCMOSD
19
CFG_IN1
I
LVTTL/ LVCMOSD
20
CFG_IN2
I
LVTTL/ LVCMOSD Schmitt Trigger
21
CFG_IN3
I
LVTTL/ LVCMOSD
22
CFG_IN4
I
LVTTL/ LVCMOSD
23
CFG_IN5
I
LVTTL/ LVCMOSD
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Table 3 Functional Pins (cont...)
Pin No. 24 Symbol CFG_IN6 I/O I Type LVTTL/ LVCMOSD Description Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 25 to to set the value of the odd divider, which applies a division of 1/3/5/7/9/11/13 or 15 to the otherwise selected spot frequency, on each of the four outputs OUTN/P[4:1]. It is also used to enable or disable the lock detector (pin 17 LOCKB), and to set the output pad mode (CML or PECL) for OUT3 and OUT4 as shown in Table 13. Configuration pin for setting up the device just after power-up or after a system reset (via pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just after power-up, so that the device works out whether this pin is connected to ground, power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 24 to to set the value of the odd divider, which applies a division of 1/3/5/7/9/11/13 or 15 to the otherwise selected spot frequency on each of the four outputs OUTN/P[4:1]. It is also used to enable or disable the lock detector (pin 17 LOCKB) and to set the output pad mode (CML or PECL) for OUT3 and OUT4 as shown in Table 13. Input reference clock that the PLL will phase and frequency lock to. Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz, and frequencies near to these so long as the chosen frequency remains stable to within the tracking range of 400 ppm. (See "Inputs" on page 8 and Table 10). Can accept LVPECL or LVDS or CML inputs given suitable external interface components. Partnered with pin 28. This clock or CLK2 can be automatically or manually selected as the reference clock, see Table 4. Input reference clock that the PLL will phase and frequency lock to. Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz and frequencies near to these so long as the chosen frequency remains stable to within the tracking range of 400 ppm. (See "Inputs" on page 8 and Table 10). Can accept LVPECL or LVDS or CML inputs given suitable external interface components. Partnered with pin 27. This clock or CLK2 can be automatically or manually selected as the reference clock, see Table 4. Second Input reference clock that the PLL will phase and frequency lock to. Input reference clock that the PLL will phase and frequency lock to. Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz, and frequencies near to these so long as the chosen frequency remains stable to within the tracking range of 400 ppm. (See "Inputs" on page 8 and Table 10). Can accept LVPECL or LVDS or CML inputs given suitable external interface components. Partnered with pin 31. This clock or CLK1 can be automatically or manually selected as the reference clock, see Table 4. Second Input reference clock that the PLL will phase and frequency lock to. Input reference clock that the PLL will phase and frequency lock to. Can accept 19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz, and frequencies near to these so long as the chosen frequency remains stable to within the tracking range of 400 ppm. (See "Inputs" on page 8 and Table 10). Can accept LVPECL or LVDS or CML inputs given suitable external interface components. Partnered with pin 30. This clock or CLK2 can be automatically or manually selected as the reference clock, see Table 4. Used in combination with pin 33, AUTO_SEL, either to select the CLK2 clock (high) or CLK1 clock (low) in manual control mode, or to select automatic switching mode, as described in Table 4.
FINAL
DATASHEET
25
CFG_IN7
I
LVTTL/ LVCMOSD
27
CLK1N
I
LVPECL
28
CLK1P
I
LVPECL
30
CLK2N
I
LVPECL
31
CLK2P
I
LVPECL
32
SEL_CLK2
I
LVTTL/ LVCMOSD
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Table 3 Functional Pins (cont...)
Pin No. 33 35 Symbol AUTO_SEL VCP I/O I A Type LVTTL/ LVCMOSD Analog Description Used in combination with pin 32, SEL_CLK2, to select automatic switching mode, as described in Table 4. Connection for external loop filter components. This is the differential control voltage input to the internal VCO and the internal differential charge pump output up to a level of 210 A. Connection for external loop filter components. This is the differential control voltage input to the internal VCO and the internal differential charge pump output up to a level of 210 A. Active low reset signal with pull up and Schmitt type input. Used to apply an active-low Power-on Reset (POR) signal during system initialization. Should be connected via a capacitor to ground. Additional differential input (2 kHz or 8 kHz) where the Sync signal on this input is sampled and resynchronized by clock output OUT1. The resynchronization can be configured via CFG_IN4 and CFG_IN5 to be with the rising or falling edge of output OUT1; see Table 12. Will also accept CML or LVDS signal types when used in conjunction with external biasing components as described in Figures 14 to 19. Additional differential input (2 kHz or 8 kHz) where the Sync signal on this input is sampled and resynchronized by clock output OUT1. The resynchronization can be configured via CFG_IN4 and CFG_IN5 to be with the rising or falling edge of output OUT1; see Table 12. Will also accept CML or LVDS signal types when used in conjunction with external biasing components as described in Figures 14 to 19. A sampled and therefore lower jitter and resynchronized version of the SYNC signal selected from the SYNC1 input. The clock selected on OUT1 (see pins 2 and 3) is used to perform the resynchronization. The resynchronization can be configured to be with the rising or falling edge of output OUT1; see Table 12. The maximum output frequency on OUT1 = 77.76 MHz when the Sync function is used. Inputs to control the frequency of the signal produced on pins 5 (OUT2P) and 6 (OUT2N). See Table 11. Inputs to control the frequency of signal that is produced on pins 5 (OUT2P) and 6 (OUT2N). See Table 11. Inputs to control the frequency of signal that is produced on pins 2 (OUT1P) and 3 (OUT1N). See Table 11. Inputs to control the frequency of signal that is produced on pins 2 (OUT1P) and 3 (OUT1N). See Table 11.
FINAL
DATASHEET
36
VCN
A
Analog
40
RESETB
I
LVTTL/ LVCMOSU Schmitt Trigger LVPECL
41
SYNCP
I
42
SYNCN
I
LVPECL
44
SYNC_OUT
O
LVTTL/ LVCMOS
45 46 47 48
RATE2A RATE2B RATE1A RATE1B
I I I I
LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD LVTTL/ LVCMOSD
Note...A= Analog, I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD = LVTTL/LVCMOS input with pull-down resistor.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Description FINAL DATASHEET
Either clock input may be manually or automatically selected as the reference based on the detection of clock activity at the inputs. The signals AUTO_SEL and SEL_CLK2, shown in Table 4, are used to control the input clock selection. In automatic mode the clock selection between CLK1 and CLK2 is non-revertive, i.e. if the PLL is locked onto CLK1 and CLK1 fails so that the PLL switches over to CLK2, then when CLK1 becomes operational again the PLL will not switch back to CLK1. Table 4 Input Selection Decoding
AUTO_SEL 0 0 1 1 SEL_CLK2 0 1 0 1 Selected Reference CLK1 CLK2 CLK1 AUTOMATIC SELECTION (Activity Monitor determines) Feedback Clock Internal Path Internal Path CLK2 Internal Path
The ACS8946 is a low-jitter integrated PLL for dejittering and clock rate translation, meeting the jitter requirements for SONET up to and including OC-12 (622.08 MHz) systems. It is compliant to the relevant ITU, Telcordia/Bellcore and ETSI standards for at least OC-3 (155.52 MHz) and OC-12 (622.08 MHz) - equivalent to the corresponding STM1 and 4 rates. It may also be used as an initial clock clean-up device in, for example, in OC-48 systems, where the CMU PLL in the Serializer/Framer has a suitable bandwidth. The ACS8946 can be configured for a range of applications using a minimal number of external components and is available in a small form factor QFN48 package at 7 mm x 7 mm x 0.9 mm outer dimensions. An evaluation board and GUI software is available on request for hands-on device assessment. Figure 3 Example EVB GUI Software
Configuration of expected input clock frequency, which has to be the same for both clock inputs, is set by the wiring of configuration pins described in Table 10. Unused differential inputs from CLK[2:1]N/P and SYNCN/P should be wired P to GND and N to VDD. In addition to the main clock inputs CLK1, and CLK2, a single differential SYNC input is provided.
Inputs
The ACS8946 has two LVPECL differential inputs (CLK1N/P, pins 27 and 28, and CLK2N/P, pins 30 and 31). These are programmable to accept input frequencies of 19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz. Frequencies near to these spot frequencies can also be accepted (see Table 5) so long as the chosen frequency supplied to each input remains stable to within the 400 ppm tracking range. LVDS and CML inputs can be accepted given suitable passive resistive and capacitive interface components. Phase comparisons are performed directly at the selected spot frequency rates in the internal Phase and Frequency Detector (PFD), unless GbE (Gigabit Ethernet) rates are selected for output rates, in which case the input frequencies are divided as required prior to the PFD.
Revision 3/November 2006 (c) Semtech Corp.
The permitted input frequency range either side of the selected spot frequency depends on the input clock rate. Table 5 presents the list of configurable input spot frequencies, and shows the maximum and minimum range about each input spot frequency that can be allowed as input to the device as a percentage of the configured input spot frequency. An External Feedback mode is available and may be used for greater control of phase discrepancies for example when using external buffers. In External Feedback mode the external feedback signal is received at the CLK2 input, hence CLK1 can be the only input in this mode.
Outputs
The ACS8946 has four, LVPECL or CML, differential outputs: OUT[4:1]N/P, pins 11/12, 8/9, 5/6, and 2/3. Outputs are produced in a CML or LVPECL output format on up to four outputs concurrently. Interfacing to LVDS is
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Table 5 Permitted Input Frequency Range
Selected Input Spot Frequency/ MHz Selected FEC Ratio (*or Divider Ratio using Odd Divider) Max and Min Permitted Input Frequency Expressed as a Percentage Above (+%) or Below (-%) the Selected Input Spot Frequency +% 19.44, 38.88 77.76, 155.52 125.00 156.25 1:1 5:4* 1:1 12.0 10.0 12.0 3.0 3.0 3.0 -%
FINAL
DATASHEET
configuration. Refer to the ACS8946 EVB Document and associated software. Unused outputs should be left floating with their associated VDD connected to GND. For example, if OUT4 is not required, connect VDD04 to GND and leave OUT4N and OUT4P unconnected.
Clock Multiplication
The ACS8946 provides options to multiply a 19.44 MHz input by 2, 4, 8, 16, or 32 for standard SONET SDH spot frequency configurations. 125.00 MHz dejittered output for Gigabit Ethernet (GbE/10 GbE) is also supported if 125.00 MHz is provided as the input reference, and 156.25 MHz input (for 12.5 GbE) is also supported. These rates are configured by the wiring of CFG_IN[3:2], see Table 10. If the input frequency used is a percentage away from the configured spot frequency, then the resulting output frequency will change by the same percentage. Refer back to Table 5 for permitted input frequencies.
Note...GbE rates are not directly available as conversions from SONET/SDH rates.
also possible using suitable passive components (see "Input and Output Interface Terminations" on page 27). Output clock rates at 19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz, 622.08 MHz or 625.00 MHz are selectable. Additionally, odd number division of these frequencies up to divide-by15 can also be configured. Note that if odd number division is used, the frequency adjustment factor will apply to all outputs, adjusting all selected output frequencies proportionally. The output frequency of each output is determined by a combination of the wiring of the configuration pins CFG_IN[7:0] read at power-up, and state of the asynchronously set RATE[2:1]A and RATE[2:1]B pins. The user configures a set of "Available Rates" (four frequencies that are available for selection at every Clock Output) and then configures each output individually to output one of these four rates. OUT1 and OUT2 are asynchronously controllable allowing the output frequency to be switched among the "Available Rates" under control from the rate selection pins (RATE[2:1]A and RATE[2:1]B). To determine the correct wiring of configuration pins to configure the device involves the use of several look-up tables, and for completeness the datasheet includes all of these, with worked examples (See "Configuration" on page 13). However, to make configuring the device much more simple than this description and look-up tables suggest, Semtech provides a user-friendly Graphical User Interface (GUI) software package to accompany the ACS8946 in which the User enters the required I/O frequencies, dividers settings etc. as required for a particular application, and the GUI responds by displaying the interconnections required to achieve that
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Voltage Controlled Oscillator
The internal VCO operates at 2.48832 GHz when the device is configured for standard SONET/SDH spot frequencies. The VCO frequency is divided down to the selected rate giving a precise 50/50 balanced mark/space ratio for the output. For 125.00 MHz operation the VCO operates at 2.500 GHz.
Jitter Filtering
Input jitter is attenuated by the PLL with the frequency cutoff point (Fc), at which jitter is either tracked or attenuated, defined by the -3 dB point i.e. the position of the first pole of the PLL loop filter. The bandwidth (frequency at which the first pole occurs) is defined by the component value selected for the filter in Tables 6 and 7. For 19.44 MHz input, using a loop filter bandwidth of 2 kHz and damping factor of 1.2 gives: High input jitter attenuation and roll off: * - 20 dB/decade from first loop filter pole, (Fc) * - 40 dB/decade from 2nd pole (typically 10 x Fc) Jitter peaking is less than 1 dB (dependent on the loop filter components)
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Typical final output jitter, e.g. 2.9 ps rms (measured over the integration range 12 kHz - 20 MHz) dictated by the ACS8946. High frequency stability when all input clocks fail; holdover frequency control to Stratum 3--dictated by the ACS8525. Typical final output jitter. e.g. 2.8 ps rms measured over the integration range of 12 kHz -20 MHz offset from carrier.
Jitter Filtering: Partnering with Semtech Line Card Protection Parts
One possible line card solution is to use the ACS8946 on the line card to provide line card protection and direct jitter filtering of references received from a Semtech SETS device (ACS8520/30) on the sync card. If a Semtech LC/P part (ACS8525) is used on the line card, another possible solution uses the ACS8946 after the Semtech LC/P part to dejitter the LC/P device's output. In the first solution, Master/Slave phase alignment on reference switchover is taken care of by a redundant pair arrangement of SETS devices, which use their output phase alignment features to ensure the ACS8946 is supplied with input clocks that are very closely tied in phase. Then, on a line card reference switch, the ACS8946 acts as a simple MUX adding negligible phase offset between the references, giving very low output disturbance for the combined system, as well as performing its dejittering function. In the second, more sophisticated solution, the reference switching capability of ACS8946 is not used, as this is carried out by the SETS or LC/P part. In both cases, the ACS8946 can be used as both an output jitter cleaner, and as a rate converter (19.44 MHz and above). One "Real World" application for the ACS8946 is to use it to dejitter the 19.44 MHz output from a Semtech ACS8525 LC/P device. In this case it is recommended to set the ACS8946 PLL bandwidth to around 2 kHz to provide a low jitter total solution. The test results detailed in the Electrical Specifications section show the "Real World" performance of this combination of parts which is a superior solution to those traditionally using simple discrete PLLs, and has the following advantages: Low overall bandwidth, 18 Hz for example--dictated by the ACS8525. High input jitter attenuation and roll-off: First, second and third order roll-off points: * - 20 dB/decade 18 Hz to 2 kHz, * - 40 dB/decade 2 kHz to 200 kHz and * - 60 dB/decade for >200 kHz.
Revision 3/November 2006 (c) Semtech Corp.
Input Jitter Tolerance
Jitter tolerance is defined as the maximum amplitude of sinusoidal jitter that can exist on the input reference clock above which the device fails to acquire/maintain lock. For the stand-alone device, the jitter tolerance is shown in Figure 4. for an undivided reference i.e. full rate PFD. For frequencies below the PLL bandwidth, jitter tolerance is seen to decrease at a rate of -20 dB per decade. For jitter frequencies above the PLL bandwidth, jitter tolerance is limited to 0.9 UI p-p.
Note...If the reference clock is divided, then the jitter tolerance will be improved.
When the ACS8946 follows an ACS8525, the input jitter tolerance is wholly defined by the ACS8525. The system jitter tolerance is dramatically increased due to the extended phase capture range of the digital PLL within the ACS8525. Figure 4 Jitter Tolerance ACS8946
Input Jitter Tolerance With 2kHz PLL Bandwidth
1000
100
Input Jitter Amplitude p-p (U I)
ACS8946 Jitter Tolerance
10
OC_12 Tolerance Mask OC_48 Tolerance Mask
1 10 100 1000 10000 100000 1000000
0.1
0.01
Jitter Frequency Offset from Carrier (Hz)
Jitter Transfer
Jitter transfer is a ratio of input jitter present on the reference clock to the filtered jitter present on the output clock. Standalone, the ACS8946 Jitter Transfer
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Characteristic is defined solely by the loop filter bandwidth and is shown in Figure 5, which shows the transfer characteristic using the recommended loop filter bandwidth of 2 kHz with a damping factor of 1.2. Figure 5 Jitter Transfer Characteristic, ACS8946 Stand-alone
1.0E+02 0
155.52 MHz output clock using an input reference of 19.44 MHz. Figure 7 Phase Noise Offset from Carrier of ACS8946 622.08 MHz output clock
Typical Phase Noise @ 155.52MHz
1.0E+03 1.0E+04 1.0E+05
Frequency (Hz)
1.0E+06 1.0E+07
ACS8946 RMS Jitter Transfer Curve ACS8944 RMS Jitter Transfer Curve
3.0
-20
(dBc/Hz)
0.0 -3.0 -6.0 -9.0 H(s) dB -12.0 -15.0 -18.0 -21.0 -24.0 -27.0 100
-40
TBIL
-60
TBIL
Phase Noise
1000 Frequency (Hz) 10000 100000
-80
-100
-120
-140
-160
In the combined solution, the ACS8525 device provides additional low frequency jitter filtering. The Jitter Transfer Characteristic of the combined ACS8946 and ACS8525 is shown in Figure 6. Figure 6 Jitter Transfer Characteristic, ACS8525 and ACS8946 combined
In the combined line card solution, the inherent jitter generated by the ACS8525 is attenuated by the ACS8946 as shown in the phase noise plot in Figure 8. Figure 8 Phase Noise Offset from Carrier, ACS8525 155.52 MHz output clock, with and without ACS8946 Clock Cleaner
Typical Phase Noise Cleaning of ACS8525
1.0E+02 -10 -30 (dBc/Hz) -50 -70 -90 -110 -130 -150 -170 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 Frequency (Hz) 1.0E+08
TBIL
Phase Noise
ACS8525 + ACS8946
ACS8525 alone
Phase Noise Performance
The inherent jitter generation by the ACS8946 is shown in the phase noise plot in Figure 7 measured on a
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Lock Detector
A simple lock detector is incorporated which combines the plus and minus phase errors from the phase detector,
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such that if any phase error signal is present, the LOCKB output drives out a +10 A current, otherwise it is off. Consequently this output (LOCKB) is a pulse width modulated (PWM) pulse stream whose mark/space ratio indicates the current input phase error. Filtering this signal with a simple external RC parallel filter as shown in Figure 9 will give a signal whose output level indicates PLL phase and frequency lock. Figure 9 Lock Filter Components
LOCK_B C1 220nF LOCKB
damping factor of 1.2 (phase margin 80.2). Higher damping factors may be used if lower transfer peaking is required. Contact Semtech Sales Support for further details.
RC Components Required to Achieve Bandwidth at Given Input Frequencies (Tables 6 to 9).
Table 6 77.76 MHz or 19.44 MHz Input Frequency
Bandwidth Closed Loop 1500 2000 56 75 150 270 R1 & R2/ 33 15 4.7 0.68 C2 & C4/ F C1 & C3 nF 200 100 33 7.5
JAM PLL
R1 470K
GND
F8944_011Lockfilter_02
4000 8000
The filtering components are external so that the time to indicate lock or not locked can be optimized for the application. The output indicates both phase and frequency lock. During off-frequency conditions the LOCKB output will be predominately high in its PWM generation with the filtered version giving a constant high state.
Table 7 155.52 MHz or 38.88 MHz Input Frequency
Bandwidth Closed Loop 1500* 2000 4000 8000 R1 & R2/ 110 150 300 560 15 6.8 2.2 0.47 C2 & C4/ F 91 47 15 3.9 C1 & C3 nF
PLL Bandwidth Setting
The bandwidth is set by two identical sets of passive RC components that connect to the differential charge pump outputs and internal VCO control inputs. Pins VCN and VCP are the combined differential charge pump outputs and VCO control voltage inputs. Figure 10 shows the arrangement. Figure 10 Loop Filter Components
JAM PLL
Note...* not available at 155.52 MHz input
Table 8 125 MHz Input Frequency
Bandwidth Closed Loop 1500 68 91 180 360
VCP VCN
R1 & R2/ 22 15
C2 & C4/ F
C1 & C3 nF 150 91 20 6.2
R1 C1 C2 C3
R2 C4
2000 4000 8000
3.3 0.68
F8943_010Loopfilter_02
GND
All capacitors should be low leakage and low ESR (Equivalent Series Resistance). Tantalum, or ceramic where possible, are suitable. Tables 6 to 9 are based on a
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Note...All bandwidths are subject to 20% variation due to component tolerancing.
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Table 9 156.25 MHz Input Frequency
Bandwidth Closed Loop 2000 4000 8000 75 150 270 R1 & R2/ 15 4.7 0.68 C2 & C4/ F C1 & C3 F 100 33 7.5
FINAL
DATASHEET
Source Switching - State Diagram
Figure 11 Simplified State Diagram of Source Switching
ALARMC_CO3 = 1 ALARM1_CO0 = 0
The ACS8946 GUI software presents the configuration information in the most user-friendly manner, though the following tables can be used instead to work out the connectivity required for a particular configuration. For example, the last five columns in Table 10 give the results of the wired connections shown in the second and third columns. E.g., taking the row 7, connecting pin CFG_IN2 to VDD and CFG_IN3 to ALARM2_C01, gives an input frequency of 19.44 MHz, a highest output frequency of 622.08 MHz and configures the outputs as LVPECL.
Output Configuration
The output spot frequency selection for OUT1 is asynchronously controlled by the RATE1A/B select pins (pins 47 and 48), which select one from a set of four "Available Rates" that have been pre-selected at powerup by the wiring configuration of pins 18 and 19 (CFG_IN[1:0]). The wiring configuration of these two pins preselects a set of any four out of seven rates: 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz and disabled, which means that each of the four outputs can run independently at any one of the four pre-selected rates - chosen by the AB value in Table 11 and odd divisions thereof as defined by the start-up configuration of CFG_IN2/CFG_IN3 and/or CFG_IN6/CFG-IN7 respectively). OUT2 is asynchronously controlled by the RATE2A/B select pins (pins 45 and 46) in the same way as OUT1. Outputs OUT3 and OUT4 cannot be controlled asynchronously; the output frequency selection is controlled at power-up or on reset by a combination of the connections of CFG_IN[1:0] and CFG_IN[5:4] to either VSS, VDD, ALARM1_CO0 (pin 13) or ALARM2_CO1 (pin 14). Given the four Available Rates have been configured as described previously, which one of these four rates is available on OUT3 is then dependent on the connections of the CFG_IN4 and CFG_IN5 pins to either VSS, VDD, ALARM1_CO0 (pin 13) or ALARM2_CO1 (pin 14)--see Table 12. The method to configure the device is summarized as follows: Select the required "Available Rates" that will be made available for selection at all four outputs using CFG_IN[1:0] (See Table 11). Define the frequencies of the fixed outputs OUT3/OUT4 using CFG_IN[5:4] (See Table 12) and the required RESYNC Edge result.
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CLK 1
ALARMC_CO3 = 1 ALARM2_CO1 = 0
CLK 2
ALARM SIGNALS: ALARMC_CO3 -- Activity alarm for the currently selected clock (from PFD) ALARM1_CO0 -- Activity alarm for CLK1 ALARM2_CO1 -- Activity alarm for CLK2 F8946D_012SimpStateDiag_01
The state diagram in Figure 11 shows a simplified view of the automatic switching behavior in the presence of activity alarms. The ALARMC_CO3 signal from the PFD is used to disqualify a clock, and the signals ALARM1_CO0 and ALARM2_CO1 representing no activity on input clocks CLK1 and CLK2 respectively, are used to determine whether or not to select the remaining clock. Switching between CLK1 and CLK2 is non-revertive. With ALARMC_CO3 providing a view of the currently selected clock that is independent to ALARM1_CO0 and ALARM2_CO1 signals, source selection behavior can be more complex when these alarm signals disagree, and so the state machine is necessarily more complex than the one shown here in order to accommodate such behavior e.g. when a clock signal is disconnected for a very short period of time, or when an input clock is running at the wrong frequency. If further details are required contact Semtech Sales Support.
Configuration
A higher degree of flexibility and programmability is possible via the use of configuration pins on the device. Permanent connections made externally from CFG_IN[7:0] pins to the configuration output pins ALARM1_CO0, ALARM2_CO1, CFG_OUT2, ALARMC_CO3 or to ground or VDD set up the device.
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Define/change the frequencies of the dynamically controllable outputs OUT1/OUT2 by driving the RATE[2:1]A/B pins high or low in accordance with the AB pattern for the required frequency as given in Table 11. Using CFG_IN[3:2], select the output interface type (CML/LVPECL) for outputs OUT1 and OUT2. (See Table 10). Using CFG_IN[7:6], enable/disable LOCKB, select the required output interface type for OUT3/OUT4 and set any odd division. If odd division is not required, set to 1. (See Table 13). rows 0 to3 and 16 to 19). Now refine the selection such that OUT 3 provides 19.44 MHz output (AB=01) and a rising RESYNC edge is required - this points to row 17 only, i.e. connect CFG_IN4 to ALARM1_CO0 and connect CFG_IN5 to ALARMC-CO3. Set each of OUT[2:1] to one of these four Available Rates, as required using the rate selection pins, e.g. to set Output OUT2 to output 38.88 MHz, set RATE2A =1 and RATE2B=0. To configure an input to the required frequency of 77.76 MHz (and Output technology for OUT 1 and OUT2 only to CML), configure CFG_IN2 to GND and CFG_IN3 to CFG_OUT2 as per row 2 in Table 10. Table 13 provides the configuration information for using pins CFG_IN[7:6] to configure whether LOCKB is enabled or disabled, the value of the odd divider, and the port interface type for OUT3 and OUT4. For example, assuming LVPECL interface type is required, LOCKB is to be enabled and the output rates (set previously according to Tables 11 and 12) are to be divided by 5 to give "Available Rates" of Off, 3.888 MHz,7.776 MHz, 15.552 MHz, then use the configuration in row 9 of Table 13, i.e. wire CFG_IN6 to VDD and CFG_IN7 to ALARM2_CO1. The corresponding frequency selections made for OUT[4:1] will be divided by 5. The configuration of row 15 would be used if the odd divider is not required (i.e. set to divideby-1).
Example Configuration
Decide which set of four output rates is most appropriate for the application and look for the configuration that provides these "Available Rates" in Table 11. E.g. If 77.76 MHz, 38.88 MHz, 19.44 MHz and 0ff are required, then configuration No. 34 in Table 11 will suffice, i.e. connect CFG_IN0 to ALARMC_CO3 and connect CFG_IN1 to CFG_OUT2. To set OUT3 or OUT4 requires the additional configuration of CFG_IN4 and CFG_IN5 as given by Table 12 (which also configures RESYNC Edge). If OUT4 is required to be set to "Off", since "Off" has already been defined by previous selection as AB=00 in Table 11, then look up the 00 pattern in Table 12, under "resulting RATE 4[AB]" (giving
Table 10 Input Divider, and OUT 1 and OUT2 Output Interface Type Configurations
Row no. Wiring of Configuration Pins CFG_IN2 CFG_IN3 Output Application Required Input Frequency/ MHz Resulting Highest Available Output Frequency/MHz (when no further division is selected) 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 625.00 Output Interface Type for OUT1 and OUT2
0 1 2 3 4 5 6 7 8(i)
GND GND GND GND VDD VDD VDD VDD CFG_OUT2
ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 ALARM1_CO0
SONET/SDH SONET/SDH SONET/SDH SONET/SDH SONET/SDH SONET/SDH SONET/SDH SONET/SDH Ethernet
155.52 155.52 77.76 77.76 38.88 38.88 19.44 19.44 125.00
CML LVPECL CML LVPECL CML LVPECL CML LVPECL CML
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Row no. Wiring of Configuration Pins CFG_IN2 CFG_IN3
FINAL
Output Application Required Input Frequency/ MHz Resulting Highest Available Output Frequency/MHz (when no further division is selected) 625.00 625.00 625.00
DATASHEET
Output Interface Type for OUT1 and OUT2
Table 10 Input Divider, and OUT 1 and OUT2 Output Interface Type Configurations (cont...)
9(i) 10
(i)
CFG_OUT2 GND GND
ALARM2_CO1 ALARM1_CO0 ALARM2_CO1
Ethernet Ethernet Ethernet
125.00 156.25 156.25
LVPECL CML LVPECL
11(i) Note:
(i) Use odd divider to divide output by 5 to get 125.00 MHz output. (ii) It is not possible to have 125.00 MHz and 625.00 MHz concurrently on separate outputs.
Table 11 Output Configuration and Selection
Row no. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM2_CO1 ALARM2_CO1 Wiring of Configuration Pins CFG_IN0 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD CFG_IN1 AB = 11 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 "Available Rates" and Associated "AB" Values (see note[i]) AB = 10 311.04 311.04 311.04 311.04 311.04 311.04 311.04 311.04 311.04 311.04 155.52 155.52 155.52 155.52 155.52 155.52 77.76 77.76 77.76 38.88 AB = 01 155.52 155.52 155.52 155.52 77.76 77.76 77.76 38.88 38.88 19.44 77.76 77.76 77.76 38.88 38.88 19.44 38.88 38.88 19.44 19.44 77.76 38.88 19.44 Off 38.88 19.44 Off 19.44 Off Off 38.88 19.44 Off 19.44 Off Off 19.44 Off Off Off AB = 00
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Row no. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Wiring of Configuration Pins CFG_IN0 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 CFG_IN1 ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 AB = 11 311.04 311.04 311.04 311.04 311.04 311.04 311.04 311.04 311.04 311.04 155.52 155.52 155.52 155.52 77.76
FINAL
DATASHEET
Table 11 Output Configuration and Selection (cont...)
"Available Rates" and Associated "AB" Values (see note[i]) AB = 10 155.52 155.52 155.52 155.52 155.52 155.52 77.76 77.76 77.76 38.88 77.76 77.76 77.76 38.88 38.88 77.76 77.76 77.76 38.88 38.88 19.44 38.88 38.88 19.44 19.44 38.88 38.88 19.44 19.44 19.44 AB = 01 38.88 19.44 Off 19.44 Off Off 19.44 Off Off Off 19.44 Off Off Off Off AB = 00
Notes: (i) Use the "Available Rates" columns as follows: Select a row of 4 "Available Rates", then, to assign any one of these four frequencies to a particular output, read off the AB value associated with that frequency and apply this value to the rate selection pins or internal signals for that output, e.g. set as High(1) or Low (0) the signals on pin pairs RATE1A and RATE1B for OUT1, RATE 2A and RATE2B for OUT2, and internal signal pairs RATE3A and RATE3B for OUT3, and RATE4A and RATE4B for OUT4. (ii) Available Rates shown assume standard SONET rates and no odd dividers.
Table 12 SYNC Edge and Clock Output Configurations
Row No. 0 1 2 3 4 5 6 7 Wiring of Configuration Pins CFG_IN4 GND GND GND GND GND GND VDD VDD CFG_IN5 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD RESYNC Edge Result Falling Falling Falling Falling Falling Falling Falling Falling 0 0 0 0 0 0 0 0 Resulting RATE4[AB] 4A 0 0 0 0 1 1 1 1 4B 0 0 1 1 0 0 1 1 Resulting RATE3[AB] 3A 0 1 0 1 0 1 0 1 3B
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Row No. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Wiring of Configuration Pins CFG_IN4 VDD VDD VDD VDD ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 ALARMC_CO3 ALARMC_CO3 CFG_IN5 ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD RESYNC Edge Result Falling Falling Falling Falling Falling Falling Falling Falling Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising Rising 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FINAL
Resulting RATE4[AB] 4A 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
DATASHEET
Resulting RATE3[AB] 3A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3B
Table 12 SYNC Edge and Clock Output Configurations (cont...)
Table 13 LOCKB, Output Technology for OUT3 and OUT4, and Odd Divider Configurations
Row No. 0 1 GND GND Wiring of Configuration Pins CFG_IN6 GND VDD CFG_IN7 Output Interface Type for OUT3 and OUT4 LVPECL LVPECL Disable Disable LOCKB Odd DIvider
3 5
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Row No. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GND GND GND GND VDD VDD VDD VDD VDD VDD ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 ALARMC_CO3 ALARMC_CO3 Wiring of Configuration Pins CFG_IN6 CFG_IN7 ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD
FINAL
Output Interface Type for OUT3 and OUT4 LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML CML Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable LOCKB
DATASHEET
Odd DIvider
Table 13 LOCKB, Output Technology for OUT3 and OUT4, and Odd Divider Configurations (cont...)
7 9 11 13 15 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 1
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Row no. Wiring of Configuration Pins CFG_IN0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND CFG_IN1
FINAL
DATASHEET
Table 14 Output Configuration and Selection for Ethernet Rates (156.25 MHz or 125 MHz input)
"Available Rates" and Associated "AB" Values (See Note (i)) AB = 11 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 625.00 312.50 312.50 312.50 312.50 312.50 312.50 312.50 312.50 312.50 312.50 156.25 AB = 10 312.50 312.50 312.50 312.50 312.50 312.50 312.50 312.50 312.50 312.50 156.25 156.25 156.25 156.25 156.25 156.25 78.13 78.13 78.13 39.06 156.25 156.25 156.25 156.25 156.25 156.25 78.13 78.13 78.13 39.06 78.13 AB = 01 156.25 156.25 156.25 156.25 78.13 78.13 78.13 39.06 39.06 19.53 78.13 78.13 78.13 39.06 39.06 19.53 39.06 39.06 19.53 19.53 78.13 78.13 78.13 39.06 39.06 19.53 39.06 39.06 19.53 19.53 39.06 AB = 00 78.13 39.06 19.53 Off 39.06 19.53 Off 19.53 Off Off 39.06 19.53 Off 19.53 Off Off 19.53 Off Off Off 39.06 19.53 Off 19.53 Off Off 19.53 Off Off Off 19.53
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Row no. Wiring of Configuration Pins CFG_IN0 31 32 33 34 Note: ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 CFG_IN1
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DATASHEET
Table 14 Output Configuration and Selection for Ethernet Rates (156.25 MHz or 125 MHz input) (cont...)
"Available Rates" and Associated "AB" Values (See Note (i)) AB = 11 156.25 156.25 156.25 78.13 AB = 10 78.13 78.13 39.06 39.06 AB = 01 39.06 19.53 19.53 19.53 Off Off Off Off AB = 00
(i) Odd divider = 1 (see Table 13)
Table 15 Output Configuration and Selection for Ethernet Rates (156.25 MHz or 125 MHz input)
Row no. Wiring of Configuration Pins CFG_IN0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM1_CO0 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 ALARM2_CO1 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 CFG_IN1 "Available Rates" and Associated "AB" Values (See Note (i)) AB = 11 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 125.00 62.50 62.50 62.50 AB = 10 62.50 62.50 62.50 62.50 62.50 62.50 62.50 62.50 62.50 62.50 31.25 31.25 31.25 31.25 31.25 31.25 15.63 15.63 15.63 7.81 31.25 31.25 31.25 AB = 01 31.25 31.25 31.25 31.25 15.63 15.63 15.63 7.81 7.81 3.91 15.63 15.63 15.63 7.81 7.81 3.91 7.81 7.81 3.91 3.91 15.63 15.63 15.63 AB = 00 15.63 7.81 3.91 Off 7.81 3.91 Off 3.91 Off Off 7.81 3.91 Off 3.91 Off Off 3.91 Off Off Off 7.81 3.91 Off
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Row no. Wiring of Configuration Pins CFG_IN0 23 24 25 26 27 28 29 30 31 32 33 34 Note: ALARM2_CO1 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 CFG_OUT2 ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 ALARMC_CO3 CFG_IN1 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2 ALARMC_CO3 GND VDD ALARM1_CO0 ALARM2_CO1 CFG_OUT2
FINAL
DATASHEET
Table 15 Output Configuration and Selection for Ethernet Rates (156.25 MHz or 125 MHz input) (cont...)
"Available Rates" and Associated "AB" Values (See Note (i)) AB = 11 62.50 62.50 62.50 62.50 62.50 62.50 62.50 31.25 31.25 31.25 31.25 15.63 AB = 10 31.25 31.25 31.25 15.63 15.63 15.63 7.81 15.63 15.63 15.63 7.81 7.81 7.81 7.81 3.91 7.81 7.81 3.91 3.91 7.81 7.81 3.91 3.91 3.91 AB = 01 3.91 Off Off 3.91 Off Off Off 3.91 Off Off Off Off AB = 00
(i) Odd divider = 5 (see Table 13)
Output Jitter
The output jitter meets all requirements of ITU, Telcordia and ETSI standards for SONET rates up to 622.08 MHz (OC-12/STM-4). See the "Electrical Specifications" sections for details on the jitter figures across the different output jitter frequency bands relevant to each specification. The recommended bandwidth of around 2 kHz is suitable for both meeting the specification on output jitter generation requirements and for filtering out the input jitter from the input clock.
Layout Recommendations
It is highly recommended to use a stable and filtered 3.3 V power supply to the device. A separate filtered power and ground plane is recommended with supply decoupling capacitors of 10 nF and 100 pF utilizing good high frequency chip capacitors (0402 or 0603 format surfacemount package) on each VDD. Good differential signal layout on the input and output lines should be used to ensure matched track impedance and phase. Contact Semtech directly for further layout recommendations.
System Reset
After power-up or a system reset via the RESETB (pin 40), the internal control logic waits for the presence of an input signal of approximately the correct frequency (at least 40% of the nominal) and then allows a further settling time of 60 ms before allowing internal frequency tuning, frequency-locking and phase-locking on to the input clock. Consequently reset should be removed only when the input frequency is within 400 ppm of the nominal frequency.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Applications FINAL DATASHEET
frequency translation of the output clocks from a Semtech Line Card Protection device. Figure 13 shows a non-specific example schematic which represents a generic line card design, and demonstrates the I/O connections, configuration controls on the device and the appropriate terminations in different CML/LVPECL technologies, with only the parts relevant to the handling of clocks being shown. This example could be used as a solution for less stringent applications where the ACS8946 could carry out the basic clock protection function in place of a Semtech Line Card Protection device, although it could not, for example, perform group (Clock and Sync) switching, frequency monitoring, or other functions available with members of the Semtech LC/P family of parts.
The ACS8946 is targeted at applications requiring clock cleaning, where input jitter is filtered out or attenuated at frequencies above the ACS8946 PLL bandwidth, and at those requiring protection switching. It also performs the function of a clock multiplying unit (CMU) translating from one common spot frequency to one of six spot frequencies (and/or odd divisions thereof) independently on each of its four outputs. The ACS8946 can save space when compared with discrete analog + VCXO solutions or module-based solutions. In the example in Figure 12 the ACS8946 is shown symbolically as a line card dejittering and clock multiplying device, providing additional jitter cleaning and
Application Diagram
Figure 12 Typical Application for Semtech JAM PLLs
Multiple Line cards
Line Card (0C-12)
Recovered Clock Sync
ACS8946
Sync
FRAMER
SERDES
Master Clock Slave Clock
JAM PLL with PROTECTION SWITCH
4 x Programmable Clocks Low Jitter/Low Skew Low Jitter spot frequencies to 625.00 MHz
To/from SONET/SDH/PDH Network
Backplane Slave Sync Card
Master Sync Card
Input CLK Sources
Config. Priorities uP/Serial Bus SSM Primary Ref. Input/ output Slave Clock Master Clock CLK Line I/F Unit DATA DATA SEC SSM Processing Priorities TCLK
SETS
ACS8510 ACS8520 ACS8522 ACS8530
Output CLKs
Clock Distribution
SetsLinecardGenApp_11
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Example Schematic FINAL DATASHEET
Figure 13 Generic Line Card Clock Source with Protection - Example Schematic
UPSTREAM DEVICE (e.g. SETS function)
CLK2 CLK1
SYNC
Transmission Line
Transmission Line
Transmission Line
R3 82R R4 82R R5 82R R6 82R Source Selection AGND CLK1 C1 AGND Loop Filter Components (place as close as possible to device pins) EXT. FB. R1 + VDDA AGND C5 10nF R2 + VDDA2 R29 Zero Ohm Link C6 100pF CLK2 VDDA SW1
R7 130R R8 130R R9 130R R10 130R
REFERENCE CLOCK INPUT to ACS8946 (Differential) VDDA
SYNC CLOCK INPUT to ACS8946 (Differential) R32 130R R31 82R R30 82R R33 130R VDDA
VDDA2 C7 10nF
AUTO C8 10nF C9 100pF
C2
C3
C10 100pF C4 Outputs from Input Activity Alarms: ALARMC ALARM2 ALARM1 VDDA LOCKB
AGND
AGND2 VDDA C25 100pF C23 10nF C24 AGND 100nF SW4 RESET AGND2 R28 10K C22 100uF
DOWNSTREAM DEVICE SYNC CLOCK OUTPUT (Single ended)
C20 100pF VDDA
C21 10nF
SW3 (Rate2A Rate2B) SW2 (Rate1A Rate1B)
37 IC1 38 VDDOSC 39 VSSOSC 40 RESETB 41 SYNCP 42 SYNCN 43 VDDP2 44 SYNC_OUT 45 RATE2A 46 RATE2B 47 RATE1A 48 RATE1B (PIN 49)
VCN 36 VCP 35 VDDARF 34 AUTO_SEL 33 SEL_CLK2 32 CLK2P 31 CLK2N 30 VDDP1 29 CLK1P 28 CLK1N 27 VDDADIV 26 CFG_IN7 25
CFG_IN6 24 CFG_IN5 23 CFG_IN4 22 CFG_IN3 21 CFG_IN2 20 CFG_IN1 19 CFG_IN0 18 LOCKB 17 ALARMC_CO3 16 CFG-OUT2 15 ALARM2_CO1 14 ALARM1_CO0 13
R11 470KR
ACS8946
AGND
C11 220nF
AGND
AGND
CMOS RECEIVER
1 VDD01 2 OUT1N 3 OUT1P 4 VDDD2 5 OUT2N 6 OUT2P 7 VDD03 8 OUT3N 9 OUT3P 10 VDD04 11 OUT4N 12 OUT4P
OUTPUTS 3 and 4 Rate selection on Power-up OUT4 = 622.08 MHz VDDA DOWNSTREAM DEVICE
VDDA3
Instant Rate Control for OUT1 and OUT2 AB 00 01 10 11 Frequency 19.44 MHz 77.76 MHz 155.52 MHz 622.08 MHz
AGND = Logic 0 = Logic 1
R12 51R VDDA4 R13 51R R14 51R R15 51R
R26 130R LVPECL RECEIVER OUT1N OUT1P R24 82R
R27 130R
Transmission Line R25 82R Transmission Line
CML RECEIVER
AGND3 VDDA VDDA3 R16 51R DOWNSTREAM DEVICE LVPECL RECEIVER R22 130R OUT2N OUT2P R20 82R R21 82R Transmission Line R23 130R C19 C18 C17 10nF 100pF 10nF C16 C15 100pF 10nF C14 10nF C13 C12 100pF 10nF Transmission Line VDDA VDDA4 R17 51R R18 51R R19 51R
OUT3 = 19.44 MHz DOWNSTREAM DEVICE
CML RECEIVER
All decoupling capacitors to be placed as close as possible to the ACS8946 device. Where possible, star connect VDDA2 and AGND2 to clean power and ground sources.
AGND3
F8946D_021ExSchematicMG_05
Note...For optimal performance use a Low Voltage Dropout (LDO) Regulator to supply VDDA2 Revision 3/November 2006 (c) Semtech Corp. Page 23 www.semtech.com
ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Electrical Specifications Maximum Ratings
Important Note: The Absolute Maximum Ratings, Table 16, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are Table 16 Absolute Maximum Ratings
Parameter Supply Voltage (D.C.): VDD01, VDD02, VDD03, VDD04, VDDP1, VDDP2, VDDADIV, VDDARF, VDDOSC Input Voltage (non-supply pins): Digital Inputs: CFG_IN0, CFG_IN1, CFG_IN2, CFG_IN3, CFG_IN4, CFG_IN5, CFG_IN6, CFG_IN7, SELCLK2, AUTO_SEL, RESETB, RATE1A, RATE1B, RATE2A, RATE2B Input Voltage (non-supply pins) LVPECL Inputs: CLK1N, CLK1P, CLK2N, CLK2P, SYNCN, SYNCP ANALOG I/O: VCN, VCP, LOCKB Output Voltage (non-supply pins): Digital Output: ALARM1_C01, ALARM2_CO1, CFG_OUT2, ALARMC_CO3, SYNC_OUT LVPECL Outputs: OUT1N, OUT1P, to OUT 4N/P Ambient Operating Temperature Range Storage Temperature Reflow Temperature (Pb) Reflow Temperature (Pb Free) ESD HBM (Human Body Model) Latchup(iii)
(i), (ii)
FINAL
DATASHEET
not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product.
Symbol VDD VIN
Minimum -0.5 -0.5
Maximum 3.6 5.5
Units V V
VIN
-0.5
VDD + 0.5
V
VOUT
-0.5
VDD + 0.5
V
TA TSTOR TREPB TREPBFREE ESDHBM ILU
-40 -50 2 100
+85 +150 +245 +260 -
C C C C kV mA
Notes: (i) All pins pass 2kV HBM except VCN/VCP which are rated at 500 V HBM. (ii) Tested to JEDEC standard JESD22-A114. (iii) Tested to JEDEC standard JESD78.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Operating Conditions
Table 17 Operating Conditions
Parameter Supply Voltage (D.C.): VDDP1, VDDP2, VDDADIV, VDDARF, Supply Voltage (D.C.): VDDOSC Supply Voltage (D.C.): VDD01, VDD02, VDD03, VDD04. * 3.135. V min required to enable output. Supply may be connected to 0 V to disable the associated output. Ambient Temperature Range Supply Current VDDOSC Supply Current Device Total Power Dissipation. (All outputs on @625.00 MHz. Excluding power dissipation in external biasing components). Symbol VDD VDDOSC VDD Minimum 3.135 3.0 3.135 or 0 V* Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 Units V V V
FINAL
DATASHEET
TA IDD IDDOSC PTOT
-40 -
330 20 1145
+85 400 25 1390
C mA mA mW
Thermal Characteristics
Table 18 Thermal Conditions
Parameter Thermal Resistance Junction to Ambient Operating Junction Temperature Symbol JA TJCT Minimum Typical Maximum 25 125 Units C/W C
AC Characteristics
Table 19 AC Characteristics
Parameter Output to Output Skew(i) Input to Output Delay SYNC_OUT to OUT1 Delay CLKx to SYNC Set-up CLKx to SYNC Hold Input Clock Rise/Fall Time
(ii)
Symbol tOSK tPDIO tPDSO tSS tSH
Minimum 0.5 -2.9 3.2 2.8 40
Typical 0.8 0.7 3.0 50
Maximum 100 3.0 -0.4 10 1.2 1.2 5.0 60
Units ps ns ns ns ns ns ns ns ns %
(CLK1, CLK2, SYNC)
tCRF tPECLRF tCMLRF tSRF tCDF
LVPECL Output Rise/Fall Time(ii), (iii) CML Output Rise/Fall Time(ii), (iv) SYNC_OUT Rise/Fall Time(ii), (v) Input Clock Duty Cycle (CLK1, CLK2, SYNC)
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Table 19 AC Characteristics (cont...)
Parameter Output Clock Duty Cycle RESETB Pulse Width after Power-up Settling Time before Start of Frequency Tuning after RESETB High Notes: (i) Outputs running at same frequency. (ii) Rise/fall time measured 10-90%. (iii) Using output load specified in Figure 17. (iv) Using output load specified in Figure 14. (v) Using 50 Ohm load. Symbol tODC tRPW tFT Minimum 48 100 10 Typical 50 Maximum 52 60 Units % ms ms
FINAL
DATASHEET
DC Characteristics
Across all operating conditions, unless otherwise stated. Table 20 DC Characteristics: LVCMOS Input Ports with Internal Pull-down/LVCMOS Schmitt Input Port with Internal Pull-up
Parameter VIN High VIN Low Pull-down Resistor Pull-up Resistor (Schmitt Input) Input Current Symbol VIH VIL RPD RPU IIN Minimum 2 43 53 -10 Typical Maximum 0.8 108 113 +10 Units V V k k A
Table 21 DC Characteristics: LVPECL Input Port
Parameter LVPECL Input Offset Voltage Differential Inputs (Note (ii)) Input Differential Voltage LVPECL Input Low Voltage Single-ended Input (Note (i)) LVPECL Input High Voltage Single-ended Input (Note (i)) Input High Current Input Differential Voltage VID = 1.4 V Input Low Current Input Differential Voltage VID = 1.4 V Symbol VIO_LVPECL VID_LVPECL VIL_LVPECL_S VIL_LVPECL_S IIH_LVPECL IIL_LVPECL Minimum VDD-2.0 0.1 VSS VDD-1.3 -10 -10 Typical Maximum VDD-0.5 1.4 VDD-1.5 VDD +10 +10 Units V V V V A A
Notes: (i) Unused differential input terminated to VDD-1.4 V. (ii) Both pins must remain within the supply voltage, i.e. >VSS and Revision 3/November 2006 (c) Semtech Corp.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Table 22 DC Characteristics: CML Output Port
Parameter IOUT current source Single-ended output voltage amplitude with 50 load to VDD and 50 input impedance into next stage. Differential output voltage amplitude with 50 load to VDD and 50 input impedance into next stage on both pins. Symbol IOUT VOS VOD Minimum 13.3 Typical 16 400 800 Maximum 19.2 Units mA mV mV
FINAL
DATASHEET
Table 23 DC Characteristics: LVPECL Output Port
Parameter LVPECL Output Low Voltage (Note (i)) LVPECL Output High Voltage (Note (i)) LVPECL Output Differential Voltage (Note (i)) Note: (i) With a 50 ohms load on each pin to VDD -2V Symbol VOL_LVPECL VOH_LVPECL VOD_LVPECL Minimum VDD-2.1 VDD-1.45 0.37 Typical Maximum VDD-1.62 VDD-0.88 1.22 Units V V V
Table 24 DC Characteristics: LVTTL/CMOS Output Port
Parameter Output Low Voltage @ IOL (MAX) Output High Voltage @ IOH (MIN) Low Level Output Current @ VOL = 0.4 V High Level Output Current @ VOH = 2.4 V Symbol VOL VOH IOL IOH Minimum 2.4 2 2 Typical Maximum 0.4 Units V V mA mA
Input and Output Interface Terminations
Interfacing to either the same type or electrically different interface types is illustrated by the following circuit diagrams in Figures 14 to 19. In applications where the output clocks are always running, they may be A.C. coupled, allowing the receive end to be at any common mode voltage, however, the lines must always be terminated at their characteristic impedance. The preferred termination for the CML type output is 50 to VDD, as shown in Figure 14. A.C. coupling may be used subsequently to translate the levels to other interface types, e.g. to LVPECL/LVDS as shown in Figure 15. The example of Figure 17 shows LVPECL to LVPECL terminations with D.C. coupling, so that the ACS8946 sees an equivalent load of around 50 from the resistor
Revision 3/November 2006 (c) Semtech Corp.
arrangement at the receiver end. Note that signal levels given in the accompanying graph are nominal levels at 622.08 MHz, and will change with load. The preferred termination circuitry for the LVDS signals between the ACS8525/26/27 and the ACS8946 LVPECL is shown in Figure 19. The bias for the LVPECL input is set for A.C. inputs at a mid point of approximately 2 V (with a 3.3 V VDD), as opposed to a normal D.C. coupled bias of VDD - 2 V. This is due to the push-pull nature of an A.C. coupled signal. Note: Where inputs to the ACS8946 are AC coupled, problems may be experienced with activity detection. This is due to noise/cross-talk on the inputs being interpreted as activity. To avoid this, DC couple wherever possible and if AC coupling must be used, consider offsetting the DC bias of the N and P signals, see Figure 16.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Figure 14 CML Output - DC Coupled to CML Receiver
FINAL
DATASHEET
Figure 16 Generic CML Output AC Coupled to LVPECL Receiver
VDD VDD
VDD
50R
50R OUTP
50R
VDD These resistors may be integrated on-chip 50R
50R
50R 82R 220nF Transmission Line OUTN 220nF
82R
OUTN Transmission Line
CML Receiver
OUTP
ACS8946 or similar LVPECL/LVDS receiver 130R 120R
OUTP VDD VDD -0.2V VDD -0.4V
VSS 16mA
16mA VSS ACS8946 output or similar CML output
VSS ACS8946 output or similar CML output
F8946D_015CML2CMLTerm_03 F8946D_014GCML2LVPECLLVDS_03
Figure 15 JAM PLL CML Output DC coupled to LVPECL or LVDS Receiver
130/120R mismatch is used in the input bias network in Figure 16 to emulate a simplified differential Schmitt trigger, reducing the susceptibility to input noise when no input is connected. Figure 17 LVPECL Output - DC Coupled to LVPECL or LVDS Receiver
VDD
VDD These resistors may be integrated on-chip
50R
50R OUTP OUTN
130R Transmission Line
130R
ACS8946 or similar LVPECL/LVDS receiver 82R 82R
ASC8946 or similar LVPECL Output VDD VDD These resistors may be integrated on-chip
VSS 16mA OUTN VSS ACS8946 output or similar CML output
F8946D_016CML2LVPECLLVDS_03
130R OUTP Transmission Line
130R
OUTP VDD -1.0 V VDD -1.4 V VDD -1.8 V
ACS8946 or similar LVPECL/LVDS receiver
82R
82R
VSS Time
F8946D_017LVPECL2LVPECLLVDS_03
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Figure 18 SETS LVDS Output - DC Coupled to LVPECL Receiver
FINAL
DATASHEET
Figure 19 Generic LVDS - AC Coupled to LVPECL Receiver
VDD
LVDS Output Device 220nF
2K7 2K7 LVPECL INPUT
JAM PLL
CLKN
SETS LVDS Output OUTN OUTP
OUTN
JAM PLL
LVPECL INPUT Transmission Line Impedance 50 Ohms CLKN CLKP
OUTP
Transmission Line Impedance 50 Ohms
CLKP 100R 220nF
100R
4K3 4K3
F8946D_018LVDS2LVPECL_02
F8946D_019LVDS2LVPECL_02
GND
Note...Activity monitors will not function with this scheme as noise may cause activity detection by mistake. Consider replacing one 4K3 resistor with a 4k7 resistor.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Jitter Performance FINAL DATASHEET
Table 25 Output Jitter Generation: ACS8946 Stand-alone @155.52 MHz Input/155.52 MHz Output
Test Definition Specification Interface Frequency Filter Spec (iv) 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps STM-16 2.5 GHz 1 MHz to 20 MHz 0.1 UI p-p = 40 ps * * * * * * 5.1 0.5 110.4 11.0 3.2 0.3 82.4 8.2 3.7 0.4 33.7 3.4 * 5.1 0.5 * 18.1 1.8 * 18.2 1.8 * 18.4 1.8 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 18.1 1.8 18.2 1.8 * 33.7 3.4 * 3.7 0.4 Typical 12.5 1.2 302.8 30.3 5.3 0.5 213.0 21.3 6.3 0.6 90.3 9.0 12.5 1.2 52.4 5.2 47.9 4.8 48.4 4.8 52.4 5.2 47.9 4.8 90.3 9.0 6.3 0.6 Measured Results Max Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
STM-1 (optical) G.813 155 MHz Option 1[4], and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8946 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications Revision 3/November 2006 (c) Semtech Corp. Page 30 www.semtech.com
ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Test Definition Specification Interface Frequency Filter Spec 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz
(iv)
FINAL
Measured Results Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps * * * * 5.1 0.5 102.6 10.3 3.2 0.3 76.6 7.7 * 3.7 0.4 * 32.7 3.3 * 5.1 0.5 * 17.5 1.7 * 17.6 1.8 * 17.8 1.8 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 17.5 1.7 17.6 1.8 * 32.7 3.3 * 3.7 0.4 Typical 12.3 1.2 281.3 28.1 5.4 0.5 197.8 19.8 6.2 0.6 87.5 8.7 12.3 1.2 50.8 5.1 46.4 4.6 46.9 4.7 50.8 5.1 46.4 4.6 87.5 8.7 6.2 0.6 Max
DATASHEET
Table 26 Output Jitter Generation: ACS8946 Stand-alone @77.76 MHz Input/155.52 MHz Output
Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
G.813 STM-1 (optical) Option 1[4], 155 MHz and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
STM-16 2.5 GHz 1 MHz to 20 MHz
0.1 UI p-p = 40 ps -
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8946 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Test Definition Specification Interface Frequency Filter Spec 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz
(iv)
FINAL
Measured Results Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps * * * * 5.3 0.5 111.1 11.1 3.3 0.3 86.9 8.7 * 3.7 0.4 * 33.7 3.7 * 5.3 0.5 * 19.3 1.9 * 19.5 1.9 * 19.6 2.0 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 19.3 1.9 19.5 1.9 * 37.3 3.7 * 3.7 0.4 Typical 12.9 1.3 304.7 30.5 5.4 0.5 224.5 22.4 6.2 0.6 100.0 10.0 12.9 1.3 56.1 5.6 51.2 5.1 51.7 5.2 56.1 5.6 51.2 5.1 100.0 10.0 6.2 0.6 Max
DATASHEET
Table 27 Output Jitter Generation: ACS8946 Stand-alone @38.88 MHz Input/155.52 MHz Output
Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
G.813 STM-1 (optical) Option 1[4], 155 MHz and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
STM-16 2.5 GHz 1 MHz to 20 MHz
0.1 UI p-p = 40 ps -
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8946 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications.
.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Test Definition Specification Interface Frequency Filter Spec 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz
(iv)
FINAL
Measured Results Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps * * * * 6.6 0.7 137.1 13.7 3.4 0.3 117.5 11.7 * 3.7 0.4 * 55.9 5.6 * 6.6 0.7 * 27.8 2.8 * 27.9 2.8 * 28.0 2.8 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 27.8 2.8 27.9 2.8 * 55.9 5.6 * 3.7 0.4 Typical 16.0 1.6 376.0 37.6 5.6 0.6 303.5 30.3 6.2 0.6 149.6 15.0 16.0 1.6 80.6 8.1 73.3 7.3 73.6 7.4 80.6 8.1 73.3 7.3 149.6 15.0 6.2 0.6 Max
DATASHEET
Table 28 Output Jitter Generation: ACS8946 Stand-alone @19.44 MHz Input/155.52 MHz Output
Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
G.813 STM-1 (optical) Option 1[4], 155 MHz and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
STM-16 2.5 GHz 1 MHz to 20 MHz
0.1 UI p-p = 40 ps -
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8946 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS
Test Definition Specification Interface Frequency Filter Spec 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz
(iv)
FINAL
Measured Results Spec Limit 0.1 UI p-p = 643 ps 0.5 UI p-p = 3215 ps 0.1 UI p-p = 161 ps 0.5 UI p-p = 804 ps * * * * 4.9 0.5 81.5 8.2 3.2 0.3 62.2 6.2 * 3.7 0.4 * 28.9 2.9 * 4.9 0.5 * 16.0 1.6 * 16.1 1.6 * 16.3 1.6 0.1 UI p-p = 643 ps 0.01 UI rms = 64.3 ps * * 16.0 1.6 16.1 1.6 * 28.9 2.9 * 3.7 0.4 Typical 11.8 1.2 223.6 22.4 5.3 0.5 160.7 16.1 6.2 0.6 77.4 7.7 11.8 1.2 46.3 4.6 42.4 4.2 42.9 4.3 46.3 4.6 42.4 4.2 77.4 7.7 6.2 0.6 Max
DATASHEET
Table 29 Output Jitter Generation: ACS8946 Stand-alone @125 MHz Input/156.25 MHz Output
Units ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms ps p-p ps rms
G.813 STM-1 (optical) Option 1[4], 155 MHz and ETSI EN 300 462 7 - 1[1]
STM-4 622 MHz 250 kHz to 5 MHz 1 kHz to 5 MHz
STM-16 2.5 GHz 1 MHz to 20 MHz
0.1 UI p-p = 40 ps -
5 kHz to 20 MHz 0.5 UI p-p = 201 ps STM-1 ETSI EN 300 462 - (electrical) 155 MHz 7 - 1[1] G.813 Option 2[4] 65 kHz to 1.3 MHz 0.075 UI p-p = 482 ps 0.1 UI p-p = 643 ps -
STM-1 155 MHz 12 kHz to 1.3 MHz
STM-4 622 MHz 12 kHz to 5 MHz 0.1 UI p-p = 161 ps STM-16 2.5 GHz 12 kHz to 20 MHz GR-253CORE[8] OC-3/STS-3 155 MHz OC-12/STS-12 622 MHz OC-48/STS-48 2.5 GHz 12 kHz to 1.3 MHz 0.1 UI p-p = 40 ps
12 kHz to 5 MHz 0.1 UI p-p = 161 ps 0.01 UI p-p = 16.1 ps 5 kHz to 20 MHz 1.5 UI p-p = 600 ps 1 MHz to 20 MHz 0.15 UI p-p = 60 ps -
Notes: (i) Measured on the ACS8946 Evaluation Board using output clock OUT1, with a 0 dBm reference clock from an ESG E4400B signal generator AC coupled to CLK1. VDD = 3.0 V to 3.465 V, TA -40C to +85C. (ii) "*" Derived values using the normal Gaussian crest value ratio of 10. (iii) PLL Closed Loop bandwidth set to 2 KHz with a damping factor of 1.2. (iv) All measurement results are derived from the phase noise plots using integration ranges defined by the telecommunication standards' specifications.
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Input/Output Timing
Figure 20 Timing Diagrams
1) Output to Output Clock Skew
OUTX OUTY tOSK
FINAL
DATASHEET
2) Input to Output Delay
CLKX OUTY
tPDIO
3a) SYNC_OUT to OUT1 Delay (OUT1 Rising Edge Aligned)
tPDSO
tPDSO
SYNC_OUT OUT1
3b) SYNC_OUT to OUT1 Delay (OUT1 Falling Edge Aligned)
tPDSO
tPDSO
SYNC_OUT OUT1
4) CLK to SYNC SET UP and HOLD
CLKX SYNC
tSS
tSH
5)
Power-up Sequence
(90% VDD) VDD RESETB
tRPW tFT
Start of Frequency Tuning Algorithm
CLKX Input frequency must be within 400 ppm of nominal before releasing reset
F8946D_021IP_OPTiming_02
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Package Information
Figure 21 QFN48 Package.
FINAL
DATASHEET
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Thermal Conditions FINAL DATASHEET
Although not essential for the ACS8946, one technique that may be used to improve heat dissipation from through the large centre pad is to include a thermal landing the same size as the centre pad on the component side of the board (and one on the opposite side of the PCB) connected to analog ground using a number of thermal vias, approximately 0.33 mm diameter. These vias should be completely connected (flooded over) to the thermal landing(s) as well as to internal ground planes if using a multi-layer PCB. 3 x 3 vias pitched at 1.27 mm between via centres would be more than sufficient for the ACS8946 if this method were adopted.
The device is rated for full temperature range when this package is used with a 4-layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. As the device includes a large thermal die paddle ground connection which must be soldered to the PCB in addition to the pins, giving improved pull-off strength and thermal dissipation characteristics as well as the necessary grounding. Figure 22 Typical 48 Pin QFN PCB Footprint
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Abbreviations
CML CMU ESD ESR HBM I/O JAM PLL GbE JAM PLL LC/P LDO LVDS LVPECL OC-3/12/48 PECL PFD PLL POR p-p rms RoHS SDH SEC SETS SONET STM-1/4/16 STS-12/48 UI uP (P) VCO WEEE Current Mode Logic Clock Multiplier Unit Electrostatic Discharge Effective Series Resistance Human Body Model Input - Output Jitter Attenuating, Multiplying Phase Locked Loop Gigabit Ethernet Jitter Attenuating, Multiplying PLL Line Card Protection Low Voltage Drop-out Low Voltage Differential Signal Low Voltage (3.3 V) PECL Optical Carrier Signal Level 3/12/48 155.52 Mbps/ 622.08 Mbps/ 2.488 Gbps Positive Emitter Coupled Logic Phase and Frequency Detector Phase Locked Loop Power-On Reset peak-to-peak root-mean-square Restrictive Use of Certain Hazardous Substances (directive) Synchronous Digital Hierarchy SDH/SONET Equipment Clock Synchronous Equipment Timing source Synchronous Optical Network Synchronous Transport Module Levels 1/4/16: 155.52 Mbps/ 622.08 Mbps 2.488 Gbps (SDH) Synchronous Transport Signal Level: 12/48, 622.08 Mbps/2.488 Gbps (SONET) Unit Interval Microprocessor Voltage Controlled Oscillator Waste Electrical and Electronic Equipment (directive)
FINAL DATASHEET References and Related Standards
[1] EN 300 462-7-1 v1.1.2 (06/2001) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 7-1: Timing characteristics of slave clocks suitable for synchronization supply to equipment in local node applications [2] ETSI EN 302 084 V1.1.1 (2000-02) Transmission and Multiplexing (TM); The control of jitter and wander in transport networks [3] ITU-T G.812 (06/1998) Timing requirements of slave clocks suitable for use as node clocks in synchronization networks [4] ITU-T G.813 (08/1996) Timing characteristics of SDH equipment slave clocks (SEC) [5] ITU-T G.823 (03/2000) The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy [6] ITU-T G.824 (03/2000) The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy [7] ITU-T G.825 (03/2000) The control of jitter and wander within digital networks which are based on the Synchronous Digital Hierarchy (SDH) [8] Telcordia GR-253-CORE, Issue 3 (09/ 2000) Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria [9] Telcordia GR-499-CORE, Issue 2 (12/1998) Transport Systems Generic Requirements (TSGR) Common requirements [10] Telcordia GR-1244-CORE, Issue 2 (12/2000) Clocks for the Synchronized Network: Common Generic Criteria [11] RoHS Directive 2002/95/EC: Directive 2002/95/EC of the European Parliament and of the Council of 27 January 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equipment [12] Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC): Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE)
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Trademark Acknowledgements
Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. Telcordia is a registered trademark of Telcordia Technologies.
FINAL
DATASHEET
Revision Status/History
The Revision Status, as shown in top center of the datasheet header bar, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the Device (not the datasheet), within the design cycle. DRAFT status is used Table 30 Revision History
Revision Rev. 0.01/June 2005 Rev. 0.02/July 2005 Rev. 0.03/July 2005 Rev. 1.00/November 2005 Rev. 2.00/February 2006 Rev. 3/November 2006 All Pages All Pages All Pages All pages All pages All pages Reference
when the design is being realized but is not yet physically available, and the datasheet content reflects the intention of the design. The datasheet is raised to PRELIMINARY status when initial prototype devices are physically available, and the datasheet content more accurately represents the realization of the design. The datasheet is only raised to FINAL status after the device has been fully characterized, and the datasheet content updated with measured, rather than simulated parameter values. This is a FINAL release of the ACS8946 datasheet. Changes made for this document revision are given below.
Description of Changes First draft with outline content ahead of measured data. Completely revised. Completely revised. Updated doc to Preliminary to reflect status of device. Minor changes and additions throughout. Completely revised. Completely revised and raised to Final status.
Notes
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ACS8946 JAM PLL
ADVANCED COMMUNICATIONS Ordering Information
Table 31 Parts List
Part Number ACS8946 ACS8946T ACS8946EVB Description JAM PLL Jitter Attenuating, Multiplying Phase Locked Loop, with Protection Switch, for OC-12/STM-4 and GbE. Lead (Pb)-free packaged version of ACS8946; RoHS and WEEE compliant. ACS8946 Evaluation Board.
FINAL
DATASHEET
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech for such use. Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards- Operation of this device is subject to the User's implementation and design practices. It is the responsibility of the User to ensure equipment using this device is compliant to any relevant standards.
Contacts
For Additional Information, contact the following: Semtech Corporation Advanced Communications Products E-mail: Internet: USA: sales@semtech.com http://www.semtech.com 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 acsupport@semtech.com
FAR EAST: 12F No. 89 Sec. 5, Nanking E. Road, Taipei, 105, TWN, R.O.C. Tel: +886 2 2748 3380 Fax: +886 2 2748 3390 EUROPE: Semtech Ltd., Units 2 and 3, Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601
ISO9001
CERTIFIED
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